The invention is generally directed to a semiconductor device and in particular to an improved bit line structure and data reading circuit in a semiconductor memory device.
In semiconductor memory devices formed of MOS transistors, a mask ROM is used to write data by use of a photoetching mask in the manufacturing process. In addition, EPROM and EEPROM devices having a floating gate structure also utilize MOS transistors as the basis of the memory cell. Because mask ROM's have the simplest structure and are easiest to understand, they are used for purposes of explanation. A mask ROM's structure is shown, for example, in 1984, ISSCC DIGEST OF TECHNICAL PAPERS pages pp 146-47, 329 (FIGS. 3-4) (hereafter "the article"). Word lines are used to connect the outputs of the row decoder to input signals A7-A16 of the address signal. Each of the above word lines is divided into two components, an upward and a downward line. Then one of the divided word lines for a 512 .times.2 memory cell array is selected, becoming a high level signal. One of the 128 output lines to every upward and downward section is selected by the column decoder based on the input of address signals A0-A6 and A14 going to a high level. In addition, one of the column transmission N-channel MOS transistors goes to an ON state. As a result, one memory cell selected from the two 512.times.128 memory cells is selected by row decoder and the column decoder and connected to the sensing amplifier.
In a mask ROM, data writing is performed by using a photoetching mask in the manufacturing process. In the mask ROM described in the above referenced article, a through hole is prepared and binary data is then written based on the connection or absence of the connection between the bit line and the source (power source terminal) of a MOS transistor which forms the memory cell. In other words, binary data is written (a binary "1") or not written (a binary "0") by the creation of a MOS transistor which provides or does not provide a current path from the power source terminal, which is connected to the source electrode of the selected memory cell, through the drain electrode to the bit line and then to the sensing amplifier. The sensing amplifier determines the presence of current or the absence of a current. The greater the magnitude of the current provided to the sensing amplifier, the quicker a reading determination can be made.
Assuming a connection hole in the selected memory cell exists and the drain electrode and bit line are connected, the bit line is reduced to a low potential level when the memory cell is selected. In addition, the input-output of the MOS inverter is short circuited, thereby reducing the input to the sensing amplifier to a low level signal. Thus, the output of the third MOS inverter (the final-output of the sensing amplifier) goes to a high level. On the other hand, where there is no connection hole in the selected memory cell, and as a result there is no current passing from the bit line through the memory cell to the power source terminal, an open state results. Thus, the input of the bit line and the sensing amplifier go to a high level and, as a result, the output of the third MOS inverter goes to a low level. The output of the third MOS inverter shown in FIG. 4 on page 147 of the article is the output of the sensing amplifier.
Binary data can be written as described above by selective creation of contact holes. However, binary data can also be written utilizing the variation in the threshold values of a MOS transistor by use of ion implantation in the channel portion of a memory cell. Another method is by the selective formation of a diffusion layer in the MOS transistor.
In the one megabit mask ROM constructed in accordance with the article described above, 512 of the memory cells are connected to a single bit line. The number of cells actually connected to the bit line by the contact holes varies. However, in the maximum case, all 512 memory cells are connected to a single bit line. In each of these memory cells the bit line is connected to the drain of the MOS transistor through a contact or through hole. As a result of this arrangement, the stray capacitance in all 512 memory cells between the drain of the MOS transistor and the substrate bit line is present. Thus, at its maximum, the stray capacitance between 512 MOS transistors' drain and the substrate and the stray capacitance between the aluminum forming the bit line and the power source terminal is present. Thus, the stray capacitance in the system can become extremely large, which significantly slows down the speed of operation.
When the MOS transistors which form the memory cell are manufactured at the minimum size of the design rule, it is expected that the semiconductor memory device will have a very large number of memory cells in a very small chip area. For example, in the article, the channel width is about 3 .mu.m and the design rule is 2 .mu.m. As the MOS transistor, which forms the memory cell, becomes smaller, the admittance, or ability to pass current, of the MOS transistor is reduced, thereby increasing the memory access time.
The one megabit structure described in the article is produced with an access time which is within an acceptable range. However, as further increases in integration and miniaturization of semiconductor memory devices occurs, a further reduction in size of the channel of the memory cell which reduces the admittance of the MOS transistor and the ability to carry current will necessarily result. Further, the stray capacitance added to the bit line increases due to the expected increase in the number of memory cells which are connected to the bit line, further reducing the operating speed of the semiconductor memory device. In addition, the power consumption resulting from wiring and the stray capacitance tends to increase.
The one megabit semiconductor memory device described in the article reduces the stray capacitance on the bit line by dividing the memory cell array into two sub-arrays, placing a column transmission transistor and sensing amplifier between the two sub-arrays. However, to divide the array into a larger number of group utilizing the structure disclosed poses the need to increase the number of column transmission transistors and sensing amplifiers as well as requiring an increase in the amount of wiring regions, e.g. the sensing amplifier output lines. On an overall basis, it will cause an increase in the chip size which is costly and undesirable.
Accordingly, there is a need for an improved semiconductor memory device which is highly integrated and operates at high speed by reducing the stray capacitance of the bit line and allowing the bit line to be driven by a relatively large current even when the size of memory cell is reduced from those produced in accordance with the present state of the art of miniaturization.